== RMAP Processor == __Figure 1 - RMAP Processor IO__ [[BR]][[BR]] [[Image(blk_rmap_proc.jpg, 800px)]] [[BR]][[BR]] __Table 1 - Tx Command Generator Interface__ ||'''Signal Name'''||'''In/Out'''||'''Width'''||'''Description'''|| ||''sof''||In||1||Start of frame signal || ||''eof'' ||In||1 ||End of frame signal|| ||''data''||In||32||input data|| ||''wr_en''||In||1||data enable signal|| ||''full_flag||Out||1||rmap fifo full flag|| [[BR]] __Table 2 - RMAP Interface__ ||'''Signal Name'''||'''In/Out'''||'''Width'''||'''Description'''|| ||''addr'' ||Out ||32 ||RMAP address signals || ||''data'' ||Out ||32 ||RMAP data signals|| ||''cs'' ||Out ||1 ||chip select, active high when RMAP is being accessed|| ||''rnw'' ||Out ||1 ||Read/Write, '1' - Read, '0' - Write || ||''rd_ack'' ||In ||1 ||Read ack signal, signals end of read cycle e.g. sample read data|| ||''wr_ack'' ||In ||1 ||Write ack signal, signals end of write cycle|| ||''rd_data'' ||In ||32 ||read data, in sync with rd_ack|| ||''intr'' ||In ||1 ||Interrupt, this signal is edge-detected inside RMAP processor|| [[BR]] __Table 3 - Rx Memory Control interface__ ||'''Signal Name'''||'''In/Out'''||'''Width'''||'''Description'''|| ||''req'' ||Out ||1||request signal, hold until ack|| ||''ack'' ||In ||1||ack from Rx memory control, single clock pulse|| ||''sof'' ||Out ||1 ||start of frame, || ||''eof'' ||Out ||1 ||end of frame|| ||''data'' ||Out ||32||data|| || || || || 1st word - type field e.g. 0x2000 for generic data, 0x2001 for interrupt (sof == 1)|| || || || || 2nd word - rmap address field|| || || || || 3rd word - rmap read data field (eof == 1)|| ||''data_en'' ||Out ||1 ||data enable, high when data is valid|| [..]