| | 1 | == Memory Controller == |
| | 2 | |
| | 3 | |
| | 4 | __Figure 1 - Memory Controller IO__ |
| | 5 | [[BR]][[BR]] |
| | 6 | [[Image(rcvr_mem_ctl.jpg)]] |
| | 7 | [[BR]][[BR]] |
| | 8 | |
| | 9 | |
| | 10 | __Table 1 - Rx Application Interface__ |
| | 11 | ||'''Signal Name''' ||'''In/Out'''||'''Width''' ||'''Description'''|| |
| | 12 | ||''app_sof'' ||In ||1 ||Start-of-frame signal, indicating first word of application data|| |
| | 13 | ||''app_eof'' ||In ||1 ||End-of-frame signal, indicating last word of application data|| |
| | 14 | ||''app_data'' ||In ||32 ||Application data|| |
| | 15 | ||''app_data_en'' ||In ||1 ||Active High, data enable signal|| |
| | 16 | ||''app_rdy'' ||Out ||1 ||memory ready signal. Active High, when '1' memory is ready to receive data|| |
| | 17 | [[BR]] |
| | 18 | |
| | 19 | |
| | 20 | __Table 2 - RMAP Processor Interface__ |
| | 21 | ||'''Signal Name''' ||'''In/Out'''||'''Width''' ||'''Description'''|| |
| | 22 | ||''rmap_req'' ||In ||1 ||Active high. Signal requesting access to memory|| |
| | 23 | ||''rmap_ack'' ||Out ||1 ||Request grant signal, active high|| |
| | 24 | ||''rmap_sof'' ||In ||1 ||Start-of-frame signal, indicating first word of rmap read data|| |
| | 25 | ||''rmap_eof'' ||In ||1 ||End-of-frame signal, indicating last word of rmap read data|| |
| | 26 | ||''rmap_data'' ||In ||32 ||rmap data|| |
| | 27 | ||''rmap_data_en'' ||In ||1 ||rmap data enable, active High|| |
| | 28 | [[BR]] |
| | 29 | |
| | 30 | |
| | 31 | __Table 3 - Command Generator Interface__ |
| | 32 | ||'''Signal Name''' ||'''In/Out'''||'''Width''' ||'''Description'''|| |
| | 33 | ||''buf_valid'' ||Out ||1 ||Buffer ready signal, indicates that data is available for transmission over ethernet port|| |
| | 34 | ||''buf_ptr'' ||Out ||16 ||Pointer to buffer location|| |
| | 35 | ||''buf_size'' ||Out ||16 ||Size of buffer data in bytes|| |
| | 36 | [[BR]] |
| | 37 | |
| | 38 | |
| | 39 | __Table 4 - Memory Interface__ |
| | 40 | ||'''Signal Name''' ||'''In/Out'''||'''Width''' ||'''Description'''|| |
| | 41 | ||''mem_addr'' ||Out ||14 ||Memory address signals|| |
| | 42 | ||''mem_data'' ||Out ||32 ||Memory data signals|| |
| | 43 | ||''me_we'' ||Out ||1 ||Memory write enable|| |
| | 44 | [[BR]] |
| | 45 | |
| | 46 | __Table 5 - Tx Ethernet Interface__ |
| | 47 | ||'''Signal Name''' ||'''In/Out'''||'''Width''' ||'''Description'''|| |
| | 48 | ||''tx_done'' ||In ||1 ||Ethernet payload transmit done signal, active high|| |
| | 49 | ||''tx_size'' ||In ||16 ||Ethernet payload size, this signal is used to subtract the current read pointer to point to next buffer read location|| |
| | 50 | [[BR]] |
| | 51 | |
| | 52 | [..] |
