R3 Overview

Figure 1 - R3 Architecture Overview

R3 architecture consists of following modules :

• Ethernet Port - Ethernet framing function,
  
  • Rx - receives ethernet frames from Host. Performs CRC checking, and forwards error free payload to packet processor.
  • Tx - transmits ethernet frames to Host. Generates Ethernet header and CRC, IP payload is provided by packet processor.
    

• Packet Processor - IP layer processing
  
  • Packet classification - RMAP, Data, and other (such as ARP and DHCP packets)
  • UDP is used for board level communication e.g. RMAP and Data packets

• APP - User specific application
  

• RF Port - DAC/ADC interfacing
  

• Control Plane - RMAP and RF control
  

• Timing Control - system wide clock control using clock enables
  

From Host, we can control the hardware (RMAP read/write operations) by sending RMAP ethernet frame messages. The packet classifier classifies and forwards packets according to its type :

• RMAP packets -> RMAP Processor
• Data packets -> Tx Buffer for APP processing
• Other packets -> TCP/IP stack

For RMAP read operations, read data must be forwarded back to Host. This is accomplished by following operations :

1. RMAP Processor forwards read data to Rx Memory Controller. Note : shared access to Rx buffer with dataflow.
   
2. Generate IP and Ethernet frame for transmission back to host. Some control header information are added in the payload section for Host RMAP read synchronization.
   

The register maps associated with the control plane handle all Board related controls e.g. RF SPI, general purpose IOs, LEDs and so forth. Whereas, data plane centric register maps are maintained within the Tx and Rx Application modules. Within the APP module, we have an option of having a top level RMAP, and/or an application specific RMAP. Usually, the top level RMAP is shared among multiple applications, whereas application specific RMAPs are only designed for a particular application.

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