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- Timestamp:
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Nov 16, 2010, 9:39:43 PM (13 years ago)
- Author:
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khanhle
- Comment:
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v18
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v19
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21 | 21 | [[BR]][[BR]] |
22 | 22 | |
23 | | The system generator options are shown in Figure 3. Assuming that the Application module has passed the verification/simulation stage successfully, you |
24 | | may build the APP module by clicking on 'Generate'. |
| 23 | The system generator options are shown in Figure 3. Assuming that the Application module has passed the verification/simulation stages successfully, you may build the APP module by clicking on 'Generate'. Note the target directory as d:\hw\simulink\ngc_netlist, and the clock rate is set to 100MHz. |
| 24 | Once the build process has completed successfully, we should have a '''app_sub.ngc''' file which is the compiled '''APP SUB'''. Now, copy this file to the Xilinx ISE CRKit project folder e.g. d:\hw\cr_build\cr_r3_sim . |
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25 | 26 | |
26 | 27 | __Figure 3 - System Generator__ |