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- Timestamp:
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Nov 16, 2010, 9:46:37 PM (13 years ago)
- Author:
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khanhle
- Comment:
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v22
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v23
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23 | | The system generator options are shown in Figure 3. Assuming that the Application module has passed the verification/simulation stages successfully, you may build the APP module by clicking on 'Generate'. Note the target directory as d:\hw\simulink\ngc_netlist, and the clock rate is set to 100MHz. |
| 23 | The system generator options are shown in Figure 3. Assuming that the Application module has passed the verification/simulation stages successfully, you may build the APP module by clicking on 'Generate'. Note the target directory is d:\hw\simulink\ngc_netlist, and the clock rate is set to 100MHz. |
24 | 24 | Once the build process is completed, we should have a '''app_sub.ngc''' file which is the synthesized version of '''APP subsystem'''. Now, copy '''app_sub.ngc''' to Xilinx ISE CRKit project folder e.g. d:\hw\cr_build\cr_r3_sim . We are now ready to link '''app_sub.ngc''' to the framework using Xilinx ISE tool. |
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