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- Timestamp:
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Nov 17, 2010, 7:19:06 PM (13 years ago)
- Author:
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khanhle
- Comment:
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v18
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v19
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5 | 5 | |
6 | 6 | 1. Start Xilinx ISE [[BR]][[BR]] |
7 | | 2. Open CRKit project located at `d:\hw\cr_build\cr_r3_sim\'''cr_r3.ise'''` . The opened project should look like as shown in Figure 1. |
| 7 | 2. Open CRKit project located at `d:\hw\cr_build\cr_r3_sim\cr_r3.ise` . The opened project should look like as shown in Figure 1. |
8 | 8 | |
9 | 9 | __Figure 1 - ISE cr_r3 project__ |
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20 | 20 | [[BR]][[BR]] |
21 | 21 | |
22 | | 5. Generate bit file. Right-click on 'Generate Programming File' in processes window, and select run or re-run. Once this step is done, the bit file is available at `d:\hw\cr_build\cr_r3_sim\'''cr_top.bit'''` . [[BR]] |
| 22 | 5. Generate bit file. Right-click on 'Generate Programming File' in processes window, and select run or re-run. Once this step is done, the bit file is available at `d:\hw\cr_build\cr_r3_sim\cr_top.bit` . [[BR]] |
23 | 23 | |
24 | 24 | 6. Use Xilinx Impact tool to download the bit file onto the FPGA. [[BR]] |