|Version 6 (modified by 6 years ago) ( diff ),|
Table of Contents
FPGA design part of the WiSer framework aims at supporting multiple hardware platforms where different communication centric applications can be dynamically linked. The FPGA framework hence provides a static part that is platform specific, and a set of dynamic apps can be instantiated by the developer onto this static part to enable specific functions for the cognitive radio application space.
FPGA framework architecture for Zynq based platforms is as shown below. Main blocks of the framework are 1) Processor subsystem - Signle ARM Cortex A9 core is being used with dual AXI bus architecture, AXI0 for Ehternet/IP packet traffic, and AXI1 for all the other data such as hardware configuration, system control and monitoring. 2) Ethernet processing - provides Ethernet packing/unpacking functionality, and integration with AXI bus architecture. Since GigE MAC resides within the embedded CPU sub-system, DMA is therefore is used to transfer incoming and outgoing traffic between Framework and GbE MAC module. Note that the processor is not invoked for this type of data transfers; it is only used to setup the DMA transaction descriptors. 3) Packet Processor - simple packet classification/forwarding scheme based on IP/UDP. Control packets get routed to the processor core, where as data packets are forwarded to corresponding APP for further wireless layer processing. It supports a subset of VITA Radio Transport protocol.