Ongoing work in the following areas :

Firmware :

  1. Multi-clock domain synchronization e.g. adc -> sys_clk, sys_clk -> dac, eth <-> sys_clk. Will need clock enable capability support. (done)
  2. Add RMAP read ability (send ethernet frame with a RMAP read request, the response will be an ethernet going back to host) (NOT done)
  3. Redesign RMAP to work with both ISE and MATLAB. (done)
  4. Add 1Gbps Ethernet support (done)
  5. Add data frame segmentation ability for ethernet packets. Rx data may be larger than Ethernet frame size. Therefore, we will need to segment the data into multiple ethernet frames (NOT supported in R3)
  6. Integrate Rx chain into MATLAB/Simulink environment (NOT done)
  7. Update current build_fw, syn_fw and par_fw scripts to support dynamically allocated application modules (done, except syn_fw and par_fw scripts)
  8. Revisit current SVN folder structure to support multiple apps (done)
  9. Add modulator into Tx use apps e.g. muxing between SINE, AWGN and host data (NOT supported in R3)
  10. Documentation : wiki, tutorials (work in progress)
  11. Add support for Freebo and WDR e.g. RMAP, SPI read capabilities (done for SDR)

Software :


R2 -> R3 : required changes to R2 revision for migration to R3.


Last modified 7 years ago Last modified on 07/14/10 14:54:47